This invention relates to a serial input-output circuit which has a circuit input terminal supplied with an input serial bit sequence and is for use as an interface between the input terminal and a processing circuit for processing an output serial bit sequence supplied from the serial input-output circuit selectively forwardly and backwardly of the input serial bit sequence.
A prior art serial input-output circuit is described in an article contributed by G. David Forney, Jr., and Edward K. Bower to the IEEE Transactions on Communication Technology, Volume COM-19, No. 5 (October 1971), pages 821 to 835, under the title of "A High-Speed Sequential Decoder: Prototype Design and Test". In the manner which will later be described a little more in detail, the prior art serial input-output circuit comprises an input shift register supplied with the input serial bit sequence for producing a sequence of output bit groups, each consisting of a first predetermined number of parallel bits. A memory device is used to memorize the parallel bits of the output bit groups as parallel bits of memorized bit groups. A producing arrangement includes a series connection of first and second bidirectional or right-left shift registers and is connected to the memory device to produce a predetermined part of the memorized bit groups as the output serial bit sequence forwardly and backwardly as regards time relative to the input serial bit sequence.
Each of the first and the second (bidirectional) shift registers may have a memory capacity for one memorized bit group. A first selected one of the memorized bit groups is read bit parallel from the memory device into a parallel-to-series converter. Through the converter and an intermediate selector having one of two input terminals connected to the converter and a single output terminal connected to the first shift register, the parallel bits of the first selected bit group are stored in bit series or sequence in the first shift register. It is possible while shifting the parallel bits in bit series forward from the first shift register to the second one to successively store the parallel bits of a second selected one of the memorized bit groups in bit series from the converter in the first shift register. In this manner, the parallel bits of two memorized bit groups are held as total held bits at a time in the first and the second shift registers.
Ordinarily, the second selected bit group next follows the first selected bit group in the input serial bit sequence. The total held bits are therefore arranged in the first and the second shift registers from an earliest bit to a latest bit. More particularly, the earliest bit is one of the parallel bits of the first selected bit group that is earliest stored in the first shift register from the converter. The latest bit is one of the parallel bits of the second selected bit group that is latest stored in the first shift register from the converter. While subjected to a forward shift from the first shift register to the second one, the held bits are delivered from the second shift register to the other of the two input terminals of the intermediate selector and from the intermediate selector to the first shift register. In this manner, the total held bits are circulated through the first and the second shift registers and the intermediate selector with the latest bit followed by the earliest bit.
Let it be assumed that a second predetermined number of output serial bits should be produced as the output serial bit sequence, through a circuit output terminal connected to a point of connection between the first and the second shift registers, starting at a predetermined one of the total held bits forwardly along the input serial bit sequence. If the latest bit is covered by the second predetermined number of bits, the memory device and the intermediate selector must be controlled to supply the first shift register in bit series with the parallel bits of a third selected one of the memorized bit groups that next follows the second selected bit group.
On subjecting the total held bits to a backward shift from the second shift register to the first one, the intermediate selector is not used. The total held bits are merely repeatedly circulated through the second and the first shift registers with the earliest bit followed by the latest bit.
Let it now be assumed that a third predetermined number of output serial bits should be produced as the output serial bit sequence through the circuit output terminal, starting at a preselected one of the total held bits backwardly along the input serial bit sequence. If the earliest bit is covered by the third predetermined number of bits, the first and second bidirectional shift registers are forced to shift forwardly by the fourth predetermined number of bits.
In this manner, once memorized bit group is read out from the memory device, a fourth one of the memorized bit groups that next preceds the memorized bit group. Namely, this serial input-output circuit has a limited value when the first and second bidirectional shift registers shift backwardly. It is possible to vary the limited value either by giving a large memory capacity to the second bidirectional shift register or by additionally using another bidirectional shift register. This is, however, undesirable in implementing the serial input-output circuit by an integrated circuit.